The present invention relates to a method for fabricating a memory device. In particular, the present invention relates to a method for fabricating a semiconductor device wherein an insulating film instead of a photoresist film is filled between gate structures when impurity ions are injected into a semiconductor substrate of a bit line contact region, and then the insulating film is removed to expose the bit line contact region without the etched residue, thereby reducing leakage current of a cell transistor.
FIG. 1 is a simplified cross-sectional view illustrating a method for fabricating a semiconductor device.
Referring to FIG. 1, a gate insulating film 30 is formed over a semiconductor substrate 10 having a device isolation structure 20. A gate conductive layer (not shown) and a gate hard mask layer (not shown) are formed over the entire surface of the resultant. The gate hard mask layer and the gate conductive layer are etched using a gate mask (not shown) to form a gate structure 60 including a stacked structure of a gate electrode 45 and a gate hard mask layer pattern 55. Next, a photoresist film (not shown) filling up the gate structures 60 is formed, and then exposed and developed using a bit line contact mask (not shown) to form a photoresist film pattern 80 exposing the semiconductor substrate 10 of a bit line contact region 85. Impurity ions are injected into the semiconductor substrate 10 exposed at the bottom of the bit line contact region 85 by using the photoresist film pattern 80 as an ion implantation mask.
According to the above method for fabricating a semiconductor device, photoresist film residue remains at the bottom of the bit line contact region during the process for forming the photoresist film pattern that exposes the semiconductor substrate of the bit line contact region because the gap between gate structures becomes narrow as the design rule of semiconductor devices are reduced.
Accordingly, the leakage current of the device due to the photoresist film residue in the bit line contact region is generated in the subsequent ion implantation process. Unlike other mask processes, the photoresist film of the bit line contact region over and between the gate structures should be removed with an exposure and development process. Despite the excessive exposure process for a thickness of 8000 Å, the photoresist residue remains at sidewalls of the gate structure of the bit line contact region. As a result, there is a substantially reduced margin for the subsequent ion implantation process.